This page may contain stale information. Last updated: 2026-07-05
Definition
RTL (Register-Transfer Level) design automation applies software engineering patterns — version control, iterative testing, acceptance gates — to hardware description language (Verilog/SystemVerilog) development and verification.
HORIZON Paradigm Shift (2026)
Traditional approach: one-shot LLM prompting for HDL generation.
HORIZON approach: repository-level code evolution — agent iterates in git worktree until executable acceptance predicate passes (compile + simulate + coverage + assertions).
Benchmark Suites
- ChipBench: Chip design tasks
- RTLLM-2.0: RTL language model benchmark
- Verilog-Eval-v2: Verilog generation evaluation
- CVDP: Nine categories including test-plan generation, debugging, bug fixing
Open Challenges
- Reward hacking in long-turnaround evaluators
- Benchmark suites ≠ production chip tape-out complexity
- Transferable pattern beyond RTL: evaluator + acceptance gate + git history as experience buffer