NVIDIA Research introduced HORIZON, a hands-free agent framework for hardware design. It treats hardware design as repository-level code evolution. This research team exercises the register-transfer level (RTL) instantiation. A structured Markdown harness becomes a project pack. A self-contained agent loop then evolves an isolated git worktree. It commits a version only when an executable acceptance gate passes.
The research team reports 100% completion across every evaluated RTL benchmark suite. It also states plainly that agentic hardware design is not solved.
What is HORIZON?
Single-turn code generation has a clear limit on executable design tasks. Plausible Verilog is not enough for real hardware. Correctness depends on cycle-level behavior, reset conventions, bit widths, and simulator feedback.
HORIZON hosts each design problem as a version-controlled repository, not a one-shot prompt. The only required input is a structured Markdown harness. That harness carries four components: a goal, domain-knowledge directions, an evaluator specification, and an acceptance predicate.
A bootstrap agent compiles the harness into a project pack covering the agent policy, executable evaluator, acceptance predicate, version-control policy, and domain skills.
For RTL, the evaluator may include compilation, simulation, coverage extraction, and assertion or testbench checks. Problems are defined over git worktrees, not over a fixed repository type.
Paper: https://arxiv.org/pdf/2606.28279
How the Repository-Level Loop Works
After bootstrap, the loop runs without further human input. Each cycle plans a target, edits the worktree, invokes tools, and runs the evaluator. The acceptance predicate decides whether to commit the new version or log the failure.
Git is the substrate. Diffs expose proposed state changes. Commits define accepted checkpoints. Notes attach evaluator evidence. The log recovers the full trajectory.
Session reuse keeps cost down. HORIZON holds a persistent model session across iterations. The harness, project pack, and stable sources are served from the provider’s prompt cache.
Benchmark Results
The backbone is GPT-5.3, fixed for all experiments. Every result uses single-agent, hands-free mode.
The evaluation spans ChipBench, RTLLM-2.0, Verilog-Eval, and nine CVDP code- and verification-generation categories (CID 002 to 016). CVDP contains 783 human-authored problems across 13 task categories.
HORIZON reaches a 100% pass rate on every suite. The one residual miss is a ChipBench specification-harness defect, not an agent failure.
| Suite / category | Focus | Iter. 0 | Conv. iter. | HORIZON |
|---|---|---|---|---|
| ChipBench | Mixed RTL generation | 20.0 | 5 | 100.0 |
| RTLLM-2.0 | NL spec to RTL | 78.0 | 2 | 100.0 |
| Verilog-Eval-v2 | HDLBits-style Verilog | 86.2 | 2 | 100.0 |
| CVDP CID 002 | RTL code completion | 3.2 | 82 | 100.0 |
| CVDP CID 003 | NL spec to RTL | 19.2 | 24 | 100.0 |
| CVDP CID 016 | Debugging and bug fixing | 25.7 | 13 | 100.0 |
The aggregate first-iteration pass rate is 47.8%.
About 91% of all tokens are cached input. Token consumption is the more informative signal once correctness saturates — three legacy suites used 6.0M tokens; nine CVDP categories used 203.9M tokens (97.1% of total).
Strengths and Limitations
Strengths:
- One protocol covers generation, completion, and repair across whole suites.
- Framework is agnostic to the underlying generator or backbone.
- Native git makes tracing and replay essentially free.
Limitations:
- Reward-feedback interface allows over-solving or reward hacking.
- Benchmarks are controlled proxies for a broader engineering problem.
- PPA-oriented loops can take days or weeks; synthesis QoR not optimized.
The research team do not claim hardware design is solved; reward hacking and long-turnaround reward stay open.